By Chris Sanders, Ziptronix Inc.
The momentum building around 3D IC integration technology over the past few years makes it clear that this technology is going to happen — it's just a matter of when. There are three main components to 3D IC technology: through silicon via (TSV) formation; thinning; and bonding. The numerous process flows that exist for 3D integration are all related to the sequence in which these three processes occur1.
When it comes to via formation, one of the questions that must be answered is whether to form the TSV before or after the IC is completed ? i.e. "via-first" or "via-last". Several companies have developed bonding technologies for both via-first and via-last process flows as follows (Figure 1).
Figure 1: (A) Via-last and (B) Via-first technologies
In the example shown above, via-last technology (Fig 1A) is based on direct oxide bonding, where silicon dioxide on the wafer surface is used as the direct-bond interface. The oxide can be a grown thermal oxide, or a deposited oxide such as plasma-enhanced CVD TEOS. The surfaces to be bonded must be extremely smooth and flat, which is typically achieved by CMP. Direct oxide wafer bonding can be used for 3D integration of CMOS ICs in three basic configurations: face-to-face (F2F)[shown in Fig 1A], face-to-back (F2B), and back-to-back (B2B).
Via-first technology (Fig. 1B) is applicable to both Al and Cu back-end-of-line (BEOL) chips and both face-to-face and back-to face, wafer-to-wafer (W2W) or die-to-wafer (D2W) bonding 5. For example, Ziptronix's patented direct bond interconnect technology (DBI) can be implemented for D2W bonding using a standard pick-and-place machine and clean room oven, thus resulting in a low cost-of-ownership (CoO) process with high throughput. This bonding process is not limited to D2W, however, since W2W can provide higher yields and higher throughput.
The process flow shown in Figure 2 depicts wafer production where wafers are stopped at the last W or Cu via level, and a cap of Ni is used to form the interconnection pads. This is then covered with a layer of deposited oxide and CPM'ed until the Ni and oxide are co-planar. Ni is used to improve the planarity of the oxide/metal interface after CMP, which results in stronger interface bonding. In the case of Cu, the Ni layer eliminates "dishing" that can occur in Cu while in the presence of a hard oxide during CMP. It is then possible to use an oxide bonding technology to "activate/terminate" the oxide surfaces. This chemical modification allows for a strong and reliable room temperature bond.
Figure 2. Direct bond interconnect process flow.
Vias Last
In via-last technology, vias are formed after the die have been fabricated, i.e after both the front end of line (FEOL) and BEOL processes have been completed.
While direct oxide bonding is normally carried out at elevated temperatures (i.e. > 1000°C) to achieve a strong, robust bond interface, the higher temperatures required are not always compatible with processed wafers. In order to bond completed ICs, a low temperature direct bond process is essential. Direct oxide bonding often produces very high interface bond strength at low temperatures 2,3. In one embodiment, the technology (Figure 3) involves a quick plasma treatment (activation) followed by an aqueous ammonium hydroxide rinse (termination). Such activation/termination processes can be easily implemented at CMOS wafer foundries, IDMs or OSATs. Subsequent to direct bonding, vias would then be formed by etching through the top chip down to the connecting pad for the lower chip.
Figure 3. Low-temperature direct oxide bonding process.
Via-first
In via-first technology, vias are introduced into the wafers either before device formation[ (FEOL) or just before BEOL interconnect. In either case, this would occur in the fab prior to completion of the die (wafer).
Metal?metal bonding is favored by the industry for 3D IC integration because it simultaneously forms both the mechanical and electrical bond. It is also generally accepted that via-first technologies will be significantly easier to manufacture since processing is at wafer scale and the vias are shallower/smaller. However, a significant drawback for one process — copper thermal compression (CuTC) bonding — is throughput. This bonding process involves heating the bonded wafers to 350 ? 400°C for 30+ minutes under pressure, requiring that the pre-bonded wafer pair must spend considerable time at one bonding station. To address this bottleneck, commercial aligner/bonder tool manufacturers have developed multiple bonding stations, which add significant costs to these tools. Without question, the industry is looking for a lower CoO method to bond wafers for 3D integration.
The direct oxide bond is initiated in a few seconds with a standard pick-and-place tool (W2W or D2W). Wafers are subsequently batch heated in a oven to ~ 300°C to form a low resistance electrical bond at the aligned Ni-Ni interface. Since the activated/terminated oxide layers are bonded together with high strength, the Ni-Ni interface is subject to sufficient internal pressure so that when the nickel expands at elevated temperature due to higher coefficient of thermal expansion (CTE), a reliable metallic bond results. The combination of a lower cost pick-and-place tool and high wafer throughput lead to lower CoO by using this low temperature oxide bonding process.
Electrical and reliability data have been generated on structures containing 1M bonded pairs on 8µm pitch which show interface resistances <0.5ohm/µm>Table below.
Whether semiconductor companies adopt via-first or -last process sequences to implement 3D integration will ultimately depend on the specific application and the available equipment.
References
[1] P. Garrou and C. Bower, "Overview of 3D Integration Process Technology", Chapter
3 in Handbook of 3D IC Integration: Technology and Applications, P. Garrou, C.
Bower and P. Ramm Eds. , Wiley VCH, 2008.
[2] USP 7,387,944
[3] P. Enquist, "3D Integration at Ziptronix", chapter 25 in Handbook of 3D IC Integration: Technology and Applications, P. Garrou, C. Bower and P. Ramm Eds., Wiley VCH, 2008.
[4] USP 6,962,835
[5] P. Enquist, "Scalability and Low Cost of Ownership Advantages of Direct Bond
Interconnect (DBI®) as Drivers for Volume Commercialization of 3-D Integration
Architectures and Applications", MRS Fall Meeting, 2008.
Contact Chris Sanders, director of business development, Ziptronix, Inc. 919-459-2444;
